Predictive Precharging for Bitline Leakage Energy Reduction *
نویسندگان
چکیده
| As technology scales down into deepsubmicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much e ort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy also is critical. Thus, we propose a predictive precharging scheme to reduce bitline leakage energy. Results show that energy savings are signi cant with little performance degradation. Also, our predictive precharging is more bene cial in more aggressively scaled
منابع مشابه
Power - Aware High - Performance Cache Memory
iii Acknowledgements iv Abstract CMOS technology scaling in recent decades has enabled a phenomenal performance improvement in microprocessors by allowing designers to increase the level of integration at higher clock frequencies. Unfortunately, technology scaling has also created unprecedented design challenges, including, but not limited to, the devices' leakage current, the interconnect dela...
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